Within the field of semiconductor chip packaging numerous problems exist. One problem area in particular relates to yield loss due to damage of semiconductor chips during bonding to ceramic packages. This problem occurs in part due to rigid connections between ceramic packaging and silicon chips. Such rigid connections are particularly vulnerable as chip size increases. This vulnerability results from the thermal expansion mismatch between bonded materials, and it produces cracked chips or mechanical breaks in the die bond region. Large chips having sides greater than 400 mils in length are quite susceptible to this problem. As a result, it is common practice within the semiconductor chip processing and packaging industries to discourage use of bonding materials which may contribute to the overall effects of thermal stress. For example, certain bonding materials are quite rigid and do not provide stress relief between the ceramic package and a silicon chip during the heating process. Other bonding materials comprise organic material, which in some environments is unacceptable for use. Further, one of the most common bonding materials requires very high cure temperatures which, in addition to causing heat stress to delicate semiconductor chip components during the bonding process, frequently results in actual melting of a bottom portion of the chip. This melting of the bottom portion of the chip forms a weld connection with part of the die bond. This common bonding material, gold-silicon eutectic, also generates out-gassing or air bubbles during the bonding process, as well as producing moisture which may lead to other complications in the manufacturing process.
Other bonding materials also exhibit undesirable qualities for use as a die bond bonding material. For example, use of epoxy-type bonding material often results in bleedout of rosin from the bonding material during the bonding process. This bleedout results in contamination of bonding surfaces and contributes to insufficient bonding at bonding points other than at the die bond. Commonly, this bleedout phenomenon is caused by a mounted semiconductor chip being pressed down into the bonding material at the die bond region by mechanical means. The mechanical means is typically a collet or similar apparatus which grips a top or side portion of the semiconductor chip and oscillates the chip by mechanical movement in contact with the bonding material. This movement, commonly referred to as scrubbing, is designed to remove the oxides from the bonding material. Mechanical damage results when a scrubbing apparatus cracks, crushes, or chips the semiconductor chip during the scrubbing action. Yet another problem related to mechanical scrubbing during die bonding is the inaccurate final placement of the chip with respect to the die bond region. This lack of precision precludes the effective use of this die bonding technique when die bonding high-density semiconductor chips to certain packages.
Another problem relating to semiconductor chip packaging is the problem of manufacturing a semiconductor chip package bond pad design which matches the pitch and density of a semiconductor chip mounted therein. Heretofore, the package bond pad pitch has been limited by wire bond tool width. As a result, the pitch of outer lead bonds on packages has differed substantially from the pitch of the chip bond sites. When combined with prior inabilities to precisely and efficiently locate and bond the chip in the die bond pad region, multiple inefficiencies in chip manufacture have resulted.
What has been needed therefore has been improved package designs for minimizing production inefficiencies such as pitch mismatch, multiple tier designs, and chip positioning imprecision which have been heretofore not sufficiently solved.
What has been further needed has been an improved high-density bond pad design for a semiconductor chip package.
What has been further needed has been a drop-through die bond process for accurately positioning a semiconductor chip onto a die bond pad region without damaging the chip.
What has been further needed has been a reflow aligned die bond process for providing low cost and high-accuracy die bonding of a semiconductor chip to a semiconductor chip package.
Objects and advantages of the present invention in achieving these and other goals will become apparent from the following descriptions, taken in connection with the accompanying drawings. Wherein are set forth by way of illustration and example certain embodiments of the present invention.